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june 2009 FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 1 www.fairchildsemi.com FDMC8200 rev.a1 FDMC8200 dual n-channel powertrench ? mosfet 30 v, 9.5 m ? and 20 m ? features q1: n-channel ? max r ds(on) = 20 m ? at v gs = 10 v, i d = 6 a ? max r ds(on) = 32 m ? at v gs = 4.5 v, i d = 5 a q2: n-channel ? max r ds(on) = 9.5 m ? at v gs = 10 v, i d = 9 a ? max r ds(on) = 13.5 m ? at v gs = 4.5 v, i d = 7 a ? rohs compliant general description this device includes two specialized n-channel mosfets in a dual power33 (3mm x 3mm mlp) package. the switch node has been internally connected to enable easy placement and routing of synchronous buck converters. the control mosfet (q1) and synchro nous mosfet (q2) have been designed to provide optimal power efficiency. applications ? mobile computing ? mobile internet devices ? general purpose point of load mosfet maximum ratings t c = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 30 30 v v gs gate to source voltage (note 3) 20 20 v i d drain current - continuous (package limited) t c = 25 c 18 18 a - continuous (silicon limited) t c = 25 c 23 45 - continuous t a = 25 c 8 1a 12 1b - pulsed 40 40 p d power dissipation t a = 25 c 1.9 1a 2.2 1b w power dissipation t a = 25 c 0.7 1c 0.9 1d t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient 65 1a 55 1b c/w r ja thermal resistance, junction to ambient 180 1c 145 1d r jc thermal resistance, junction to case 7.5 4 device marking device package reel size tape width quantity FDMC8200 FDMC8200 power 33 13 ? 12 mm 3000 units g2 g1 bottom g2 d1 s2 s2 s2 d1 g1 d1 d1 d2/s1 s2 s2 s2 d1 d1 d1 pin 1 v i n s w i t c h n o d e g l s v i n g n d g n d g n d g h s v i n v i n v i n s w i t c h n o d e g l s v i n g n d g n d g n d g h s v i n v i n 4 3 2 1 5 6 7 8 q1 q2 4 3 2 1 5 6 7 8 q1 q2 power 33 bottom
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 2 www.fairchildsemi.com FDMC8200 rev.a1 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v i d = 250 a, v gs = 0 v q1 q2 30 30 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 250 a, referenced to 25 c q1 q2 14 14 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v v ds = 24 v, v gs = 0 v q1 q2 1 1 a i gss gate to source leakage current v ds = 20 v, v gs = 0 v q1 q2 100 100 na na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a v gs = v ds , i d = 250 a q1 q2 1.0 1.0 2.3 2.3 3.0 3.0 v ? v gs(th) ? t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 250 a, referenced to 25 c q1 q2 -5 -6 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 6 a v gs = 4.5 v, i d = 5 a v gs = 10 v, i d = 6 a, t j = 125 c q1 16 24 22 20 32 28 m ? v gs = 10 v, i d = 9 a v gs = 4.5 v, i d = 7 a v gs = 10 v, i d = 9 a, t j = 125 c q2 7.3 9.5 10 9.5 13.5 13 g fs forward transconductance v dd = 5 v, i d = 6 a v dd = 5 v, i d = 9 a q1 q2 29 56 s c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1 mhz q1 q2 495 1180 660 1570 pf c oss output capacitance q1 q2 145 330 195 440 pf c rss reverse transfer capacitance q1 q2 20 30 30 45 pf r g gate resistance q1 q2 1.4 1.4 ? t d(on) turn-on delay time q1 v dd = 15 v, i d = 1 a, v gs = 10 v, r gen = 6 ? q2 v dd = 15 v, i d = 1 a, v gs = 10 v, r gen = 6 ? q1 q2 11 13 20 23 ns t r rise time q1 q2 3.1 4 10 10 ns t d(off) turn-off delay time q1 q2 35 38 56 60 ns t f fall time q1 q2 1.3 6 10 12 ns q g(tot) total gate charge v gs = 0 v to 10 v q1: v dd = 15 v, i d = 6 a, q2: v dd = 15 v, i d = 9 a, q1 q2 7.3 16 10 22 nc q g(tot) total gate charge v gs = 0 v to 4.5 v q1 q2 3.1 7 4.3 10 nc q gs gate to source charge q1 q2 1.8 4.1 nc q gd gate to drain ?miller? charge q1 q2 1 1.5 nc
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 3 www.fairchildsemi.com FDMC8200 rev.a1 electrical characteristics t j = 25 c unless otherwise noted drain-source diode characteristics notes: 1. r t ja is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r t jc is guaranteed by design while r t ca is determined by the user's board design. 2. pulse test: pulse width < 300 p s, duty cycle < 2.0%. 3. as an n-ch device, the negative vgs rating is for low du ty cycle pulse ocurrence only. no continuous rating is implied. symbol parameter test conditions type min typ max units v sd source to drain diode forward volt- age v gs = 0 v, i s = 6 a (note 2) v gs = 0 v, i s = 9 a (note 2) q1 q2 0.8 0.8 1.2 1.2 v t rr reverse recovery time q1 i f = 6 a, di/dt = q2 i f = 9 a, di/dt = q1 q2 13 21 24 34 ns q rr reverse recovery charge q1 q2 2.3 5.6 10 12 nc a.65 c/w when mounted on a 1 in 2 pad of 2 oz copper c. 180 c/w when mounted on a minimum pad of 2 oz copper b.55 c/w when mounted on a 1 in 2 pad of 2 oz copper d. 145 c/w when mounted on a minimum pad of 2 oz copper 100 a/ s 100 a/ s
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 4 www.fairchildsemi.com FDMC8200 rev.a1 typical characteristics (q1 n-channel) t j = 25 c unless otherwise noted figure 1. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40 v gs = 10 v v gs = 4 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 3.5 v v gs = 4.5 v v gs = 6 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 10203040 0 1 2 3 4 v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 6 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.8 1.0 1.2 1.4 1.6 i d = 6 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 246810 0 20 40 60 80 100 t j = 125 o c i d = 6 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 2.0 2.5 3.0 3.5 4.0 4.5 0 10 20 30 40 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 40 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 5 www.fairchildsemi.com FDMC8200 rev.a1 figure 7. 02468 0 2 4 6 8 10 i d = 6 a v dd = 10 v v dd = 15 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 20 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 10 100200 0.001 0.01 0.1 1 10 100 10 s 1 s dc 100 ms 10 ms 1 ms 100 us i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 180 o c/w t c = 25 o c f o r w a r d b i a s s a f e operating area figure 10. 25 50 75 100 125 150 0 5 10 15 20 25 limited by package r t jc = 7.5 o c/w v gs = 4.5 v v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) maximum continuous drain current vs case temperature 10 -4 10 -3 10 -2 10 -1 110 100 1000 1 10 100 p (pk) , peak transient power (w) v gs = 10 v single pulse r t ja = 180 o c/w t a = 25 o c t, pulse width (s) 300 0.5 figure 11. single puls e maximum power dissipation typical characteristics (q1 n-channel) t j = 25 c unless otherwise noted
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 6 www.fairchildsemi.com FDMC8200 rev.a1 figure 12. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.003 0.01 0.1 1 single pulse r t ja = 180 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics (q1 n-channel) t j = 25 c unless otherwise noted
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMC8200 rev.a1 typical characteristics (q2 n-channel) figure 13. on-region characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40 v gs = 3 v v gs = 4 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 3.5 v v gs = 4.5 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) 0 10203040 0 1 2 3 4 5 6 v gs = 3 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 3.5 v v gs = 4 v v gs = 4.5 v v gs = 10 v figure 14. normalized on-resistance vs drain current and gate voltage figure 15. normalized on-resistance vs junction temperature -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 9 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 0 10 20 30 40 50 60 t j = 125 o c i d = 9 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max figure 16. on-resistance vs gate to source voltage figure 17. transfer characteristics 1.5 2.0 2.5 3.0 3.5 4.0 0 10 20 30 40 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 18. source to drain diode forward voltage vs source current 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 40 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) t j = 25 c unless otherwise noted
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 8 www.fairchildsemi.com FDMC8200 rev.a1 typical characteristi cs (q2 n-channel) t j = 25 c unless otherwise noted f i g u r e 1 9 . g a t e c h a r g e c h a r a c t e r i s t i c s f i g u r e 2 0 . c a p a c i t a n c e v s d r a i n to source voltage f i g u r e 2 1 . f o r w a r d b i a s s a f e operating area figure 22. maximum continuous drain current vs case temperature figure 22. single pulse maximum power dissipation 0369121518 0 2 4 6 8 10 i d = 9 a v dd = 10 v v dd = 15 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 20 v 0.1 1 10 30 10 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 0.01 0.1 1 10 100200 0.01 0.1 1 10 100 10 s 1 s dc 10 ms 1 ms 100 us 100 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r ja = 145 o c/w t c = 25 o c 25 50 75 100 125 150 0 10 20 30 40 50 limited by package r jc = 4 o c/w v gs = 4.5 v v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) 10 -4 10 -3 10 -2 10 -1 110 100 1000 1 10 100 1000 p (pk) , peak transient power (w) v gs = 10 v single pulse r ja = 145 o c/w t a = 25 o c t, pulse width (s) 0.5
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 9 www.fairchildsemi.com FDMC8200 rev.a1 figure 23. junction-to-ambient transient thermal response curve typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.001 0.01 0.1 1 single pulse r ja = 145 o c/w duty cycle-descending order normalized thermal impedance, z ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 10 www.fairchildsemi.com FDMC8200 rev.a1 dimensional outlin e and pad layout
FDMC8200 dual n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 11 www.fairchildsemi.com FDMC8200 rev.a1 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, us ed under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical co mponents in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi ficant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms auto-spm? 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